1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices allowing improved production yield and device characteristic control by employing laser trimming.
2. Description of the Background Art
In a semiconductor memory device having an MOS (Metal Oxide Silicon) configuration, spare memory cells are generally arranged in order to increase production yield. These replaced defective memory cells if necessary, in order to repair pattern defects caused in the manufacturing process.
Referring to and compared with cells shown in FIG. 9, a memory cell used in the present invention will be described.
With reference to FIG. 9, it is difficult to increase the capacity of a byte-erasable EEPROM (electrically erasable programmable ROM) because a select transistor included in the EEPROM increases the cell area. In an EPROM(erasable programmable ROM), writing is performed electrically and erase is performed collectively by ultraviolet radiation. As shown in the figure, a simple configuration having one transistor per one cell allows a small cell area. In a flash memory, collective erase performed by ultraviolet radiation in the EPROM is replaced by electrical erase achieved by charge ejection utilizing tunnel effect caused by the applied high electric field. As a result, non-volatility, electrical rewrite and erasure, and increased capacity can be obtained at the same time.
Among a number of approaches for the replacement of a spare memory cell, a laser trimming method (hereinafter is referred to as LT method) is commonly performed, in which a link is blown by laser radiation to replace a defective cell with a spare one. The LT method is also used for the fine control of reference voltage, for example, generated in the semiconductor device.
Conventionally a final protection film is formed after the LT blow process in order to prevent water and contamination from entering through the portion blown by LT process. In this approach, however, pattern defect which occurred in the final process after yield-enhancing LT blow cannot be corrected. Further, particle are generated at the time of LT blow, increasing pattern defect.
To solve the above mentioned problem, in some cases the LT blow process is performed after the formation of the final protection film. This case will be described referring to the figures.
FIG. 10 is a sectional view of a semiconductor device having an LT link portion (fuse portion).
Referring to FIG. 10, a P well 2 and an N well 3 are formed on the main surface of a semiconductor substrate 1. An isolation oxide film 5 is formed in the main surface of P well 2. An LT link 8 is formed on isolation oxide film 5. A gate electrode 7 is also formed on P well 2 with a gate insulation film 6 posed therebetween. At each side of gate electrode 7, are formed N type diffusion layers 10 which are to be source/drain of an N type channel transistor (NchTr).
A side wall spacer 9 is formed on the sidewall of gate electrode 7. A P type channel transistor (PchTr) is formed in N well 3. The P type channel transistor includes a gate insulation film 6, a gate electrode 7 and P type diffusion layers 11 which are to be source/drain of the P type channel transistor. An interlayer insulation film 12 formed of a BPSG film and the like is provided on semiconductor substrate 1 so as to cover gate electrode 7 and LT link 8.
A contact hole 13 is formed in interlayer insulation film 12 in order to expose the surfaces of P type diffusion layer 11, N type diffusion layer 10 and LT link 8. An interconnection 14 formed of aluminum alloy and so on is connected to LT link 8, N type diffusion layer 10 and P type diffusion layer 11 through contact hole 13. A final protection film 15 is formed on interlayer insulation film 12 so as to cover interconnection 14. Referring to FIG. 11, laser trimming of LT link 8 allows the replacement of a defective memory cell with a spare memory cell.
In the conventional system, however, as can be seen from FIG. 11, semiconductor substrate 1 is exposed at the blown LT link. Therefore water and contamination such as sodium (Na) may easily enter the semiconductor device from outside through the exposed portion. When water or contamination enters the semiconductor device region where an active element resides, characteristics of transistors may fluctuate. Especially in the case of a non-volatile semiconductor memory device such as an EPROM and a flash memory, stored content which has been retained may volatilize, and a defect may be induced leading to the reliability degradation of the semiconductor device.